Hardware Security Enhancements for Energy-Constrained Machine Learning Accelerators

Abstract

The rapid deployment of machine learning (ML) accelerators in energy-constrained environments such as edge devices, wearable technologies, and Internet of Things (IoT) platforms has intensified the demand for hardware-level security mechanisms. While energy efficiency is a primary design goal for such accelerators, it inadvertently exposes vulnerabilities that adversaries can exploit through side-channel attacks, fault injection, and hardware Trojan insertions. This paper presents an in-depth analysis of hardware security enhancements tailored for energy-constrained ML accelerators. We examine the trade-offs between security and energy consumption, emphasizing the integration of lightweight cryptographic primitives, secure memory hierarchies, and tamper-resistant architectures. Experimental evaluations were conducted on FPGA-based prototypes implementing deep neural network accelerators with integrated security modules. Results demonstrate that lightweight security primitives can achieve up to 30% energy reduction compared to conventional cryptographic methods while maintaining robust resistance against attacks. The findings suggest that balancing efficiency and trustworthiness in ML accelerators is critical to enabling secure, low-power intelligent systems at scale.